1. Field of Invention
The present invention relates to a method and an apparatus for video signal frequency multiplication, and more particularly, to a method and an apparatus for interlace scanning video signal frequency multiplication.
2. Description of Related Art
At present, image and video display devices generally all have frequency multiplication functionality. The so-called “frequency multiplication” means that the scan line for inputting video signal is increased or reduced by a magnitude, where the magnitude is not limited to an integer, and 0.5, or 1.5, etc. are also possible values. Thus, images or video frames can meet the requirements of the resolution of the display device after being processed. Taking the cathode ray tube display as an example, the video signal can be transferred in two ways, i.e., the interlace scan signal and the non-interlace scan signal. Therefore, the architecture of the video processing apparatus can be divided into the interlace scan and the non-interlace scan. If a video processing apparatus with the interlace scan architecture is employed, each of the video frames must include an odd number of scan lines; if a video processing apparatus with the non-interlace scan architecture is employed, each of the video frames must include an even number of scan lines.
FIG. 1A is a timing diagram of the conventional interlace scan. FIGS. 1B, 1C, and 1D are schematic views of the displaying modes for the conventional interlace scan. Referring to FIGS. 1A, 1B, 1C, and 1D together, the timing diagram 100 of the interlace scan includes the vertical synchronous signal (V-sync signal) and the horizontal synchronous signal (H-sync signal). During the period of the first pulse V1 of the V-sync signal, the input video frame F is scanned for the odd number of scan lines O (as shown in FIG. 1B) according to the scan period of the H-sync signal, so that an odd field OF is produced. During the period of the pulse V2 of the second V-sync signal, the input video frame F is similarly scanned for the even number of scan lines E (as shown in FIG. 1C) according to the scan period of the H-sync signal, so that an even field EF is produced.
The odd field OF and the even field EF forms a video frame F of the display device, and the video frame F includes (2n+1) scan lines SL. For example, as for the odd field OF, the electron gun of the display device only scans the odd scan lines O of the video frame F, wherein the odd field O includes (n+0.5) scan lines. As for the even field EF, the electron gun of the display device only scans the even scan lines E of the video frame F, wherein the even field EF also includes (0.5+n) scan lines. Therefore, when the odd field OF is added to the even field EF (as shown in FIG. 1D), (2n+1) scan lines SL will be produced, i.e., the image that will be finally displayed to the user by the display device. The solid arrow in FIGS. 1B, 1C, and 1D shows that the electron gun of the display device is scanning the scan lines SL, and the dashed arrow shows that it draws back.
FIG. 2 is a block diagram of the conventional video processing apparatus of the display device. Referring to FIG. 2, the video processing apparatus 200 includes an analog-to-digital converter (ADC) 201, an input synchronizing processor 203, a capture 205, a buffer 207, a frequency multiplier 209, and an output synchronizing processor 211. The buffer 207 can be a frame buffer for storing one or more frames or a scan line buffer for storing one or more scan lines.
The ADC 201 is used to receive the video signal VS, and to provide the digital signal to the capture 205. The input synchronizing processor 203 is used to receive the first composite synchronous signal H/V_Sync_in, and to provide the first H-sync signal and the first V-sync signal to the capture 205, respectively. According to the first H-sync signal and the first V-sync signal respectively, the capture 205 is used to capture the range for the digital signal to be processed, and send to the buffer 207. The buffer 207 stores the digital data in a unit of frame or scan line. After being processed by the frequency multiplier 209, the digital signal VO is output, and the second H-sync signal and the second V-sync signal are respectively output to the output synchronizing processor 211. The output synchronizing processor 211 provides a second composite synchronous signal H/V_Sync_out according to the second H-sync signal and the second V-sync signal. And finally, the video processing apparatus 200 provides the output digital signal VO and the second composite synchronous signal H/V_Sync_out to a back-end circuit of the display device for further processing.
The above-mentioned first composite synchronous signal H/V_Sync_in is produced by combining the first H-sync signal and the first V-sync signal through modulating. Correspondingly, if the first composite synchronous signal H/V_Sync_in is demodulated, the first H-sync signal and the first V-sync signal will be produced respectively. Similarly, the second composite synchronous signal H/V_Sync_out is also produced by combining the second H-sync signal and the second V-sync signal through modulating. Thus, if the second composite synchronous signal H/V_Sync_out is demodulated, the second H-sync signal and the second V-sync signal will be produced respectively.
FIG. 3A is a schematic view of the conventional frequency multiplication method employing a frame buffer. Referring to FIGS. 1A, 2, and 3A together, the buffer 207 in the video processing apparatus 200 is a frame buffer. Therefore, during the scan period t of the H-sync signal, the buffer 207 temporarily stores the scan lines SL of the odd field OF. Then, when the scan lines SL of the even field EF are received, the scan lines O of the odd field are added to the scan lines E of the even field with video frame F as a storage unit, so as to form a complete image. As such, in the same scan period t of the H-sync signal (H-sync), a frequency-multiplied output can be achieved after the processing of the frequency multiplier 209.
FIG. 3B is a schematic view of the displaying mode for the conventional non-interlace scan employing a frame buffer for frequency multiplication. Conventionally, although a desirable image can be obtained by employing a frame buffer, performing the frequency multiplication with the frequency multiplier, and outputting in a non-interlace scan mode, the cost is considerably high since the frames are stored by the frame buffer.
FIG. 4A is a schematic view of the conventional frequency multiplication method employing a scan line buffer. Referring to FIGS. 1A, 2, and 4A together, the buffer 207 in the video processing apparatus 200 is a scan line buffer. Therefore, during the scan period t of the H-sync signal, the individual scan lines SL of the odd field OF and that of the even field EF stored in the buffer 207 are together processed by the frequency multiplier 209, so that in the same scan period t of the H-sync signal (H-sync), a multiplied-frequency output can be achieved for the individual scan lines SL of the odd field OF and that of the even field EF.
FIG. 4B is a schematic view of the displaying mode for the conventional interlace scan employing a scan line buffer. After being frequency multiplied by the frequency multiplier, the odd field and the even field are output in an interlace scan mode. Each of the odd field and the even field originally include 0.5 scan lines. Due to the frequency multiplication, the number of the scan lines for both the odd field and even field becomes an integer. Thereby, the two fields forming the display image overlap when output by the display device (as shown in FIG. 4B), and the image quality is deteriorated.
In view of the above, in the conventional video frequency multiplication apparatus, the video signal can be transferred in two ways, i.e., the interlace scan signal and the non-interlace scan signal, such that the architectures of the video processing apparatus can be divided into the interlace scan and the non-interlace scan. In addition, the buffers can be categorized as the frame buffer and the scan line buffer. Although a desirable image can be achieved by employing a frame buffer, performing the frequency multiplication with the frequency multiplier, and outputting in a non-interlace scan mode, the cost is considerably high since the frames are stored by the frame buffer. On the other hand, when employing a scan line buffer, performing the frequency multiplication with the frequency multiplier and outputting in an interlace scan mode, the odd and even fields output by the display device are overlapped with each other, thus, the purpose of the interlace scan becomes meaningless; and the image quality is deteriorated.